1. Field of the Invention
The present invention relates to a method for designing a semiconductor integrated circuit. In particular, it relates to a technology for controlling a timing with respect to a voltage drop (referred to as an IR drop hereinafter) caused by a resistance component of a power supply wiring in a semiconductor integrated circuit, and a method for designing a circuit in which the effect of an IR drop is reduced.
2. Description of the Related Art
Recently, as the size of LSI has been increased and lower electric power has been demanded, various kinds of physical phenomena have become significant. Therefore, unless such physical phenomena are taken into consideration at the designing stage, a phenomenon occurs in which a semiconductor integrated circuit operates in simulation but does not operate as an actual product. In particular, a phenomenon referred to as an IR drop, caused by a resistance component of a power supply wiring, hardly was considered a problem in the era of the 0.25 μm rule in which a power supply voltage was high. However, as the structure has become increasingly finer, the power supply voltage has been lowering to 1.8V, to 1.5V and to 1.0V. Such an IR drop has not been negligible.
FIG. 11A is an equi-voltage view schematically showing a distribution of an amount of IR drop in an LSI. In FIG. 11A, since a power supply pad (not shown) is placed on the outer circumferential part of the LSI, a region 1101 in the center part of the LSI is distant from the power supply pad, so that the amount of IR drop is larger. On the contrary, in a region 1100 near the power supply pad, the amount of the IR drop is smaller.
Furthermore, an IR drop occurs significantly in a synchronous design. This is because, in the synchronous design, all flip-flops operate simultaneously in synchronization with a clock signal, and a large amount of electric current flows into a power supply wiring for providing these flip-flops with an electric power, thus causing an IR drop.
FIG. 11B is a graph showing the relationship between a cycle time and an amount of IR drop. As shown in FIG. 11B, the amount of IR drop becomes large at the rising edge of a clock signal CK and then a power supply voltage approaches an ideal power supply voltage with the passage of time.
Next, the effect of the occurrence of an IR drop will be explained.
When an IR drop occurs, since an amount of power supplied to cells constituting an LSI is reduced, the operations of the cells become slow and thus a timing change occurs. However, the present timing design is performed assuming that the power supply is an ideal power supply, that is, an IR drop does not occur. Therefore, when the timing change occurs due to this IR drop, a timing error may occur in an LSI when it is used as an actual product although it had no timing problem at the verification stage.
Conventionally, the power supply wiring is designed so as to prevent the occurrence of an IR drop. Specifically, attempts for avoiding an IR drop have been performed by increasing the number of power supply pads 1200 so as to increase the number of the power supply wirings as shown in FIG. 12A, or by employing a mesh wiring so as to increase an amount of the power supply to the center portion of an LSI as shown in FIG. 12B.
There was another method in which, assuming that an IR drop occurs inevitably, a timing change due to the IR drop was taken into a delay library used for calculating the timing. The timing design is performed by using the delay library at the time of designing. There were two kinds of approaches with this idea.
The first approach is a method including, after performing a layout, analyzing an IR drop, calculating a delay based on the amount of the IR drop and verifying the timing. FIG. 13 is a flowchart showing this designing method.
In a layout procedure S1300, a layout is performed without considering IR drop and a layout 1300 is output. Next, in an IR drop analyzing procedure S1301, for all cells constituting the LSI, an amount of IR drop 1301 is calculated from the layout 1300. Next, in a delay calculation procedure S1302, a delay calculation is performed by using a delay library 1302 considering IR drop characterized at various power supply voltages and the amount of IR drop 1301 for each cell. Herein, since it is not known how much IR drop occurs when the delay library 1302 considering IR drop is produced, it is necessary to characterize the delay with many kinds of power supply voltages. Next, in a timing verification procedure S1303, the timing verification is performed by using a delay information 1303 considering IR drop and it is determined whether or not the timing is in time.
Furthermore, there is another method including predetermining an amount of IR drop of LSI, performing a layout so that the IR drop reaches the predetermined IR drop, calculating a delay and verifying a timing. In this method, for example, 50 mV of IR drop is predetermined to occur and a layout is performed so that the IR drop becomes 50 mV. FIG. 14 is a flowchart showing this designing method.
In a layout procedure S1400 considering IR drop, a layout 1400 considering IR drop is generated so that an amount of IR drop becomes the predetermined amount. Next, in a delay calculation procedure S1401, a delay calculation is performed from a delay library 1401 considering IR drop characterized by the predetermined amount of IR drop and the layout 1400 considering IR drop, the delay information 1303 is output and then a timing verification is performed in the timing verification procedure S1303.
The above-mentioned conventional designing methods have such problems as mentioned below.
Firstly, in the design of the power supply wiring in which the number of the power supply wirings or power supply pads are increased so as to suppress the amount of IR drop, there are problems that: it is necessary to increase the number of the power supply wirings, thus reducing the effective area necessary for arrangement of elements; or the number of power supply pads is increased, thus reducing the number of pads that can be used for other than the power supply pads.
Furthermore, in the designing method shown in FIG. 13 in which the IR drop is analyzed and the delay is calculated with the amount of IR drop, at the time of producing the delay library 1302 considering IR drop, characterization at possible various power supply voltages is required for all cells and thus the time for producing the delay library becomes enormous.
Furthermore, in the designing method shown in FIG. 14 in which the layout is generated after the amount of IR drop is predetermined, it is difficult to have all cells operate with the same amount of IR drop.